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[dynarmic, loongarch64] Add minimal toy implementation enough to execute LSLS (#4054)
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/4054 Reviewed-by: Lizzie <lizzie@eden-emu.dev> Reviewed-by: crueter <crueter@eden-emu.dev>
This commit is contained in:
Yang Liu
crueter
parent
661346503b
commit
48219f348c
@ -299,10 +299,24 @@ if ("loongarch64" IN_LIST ARCHITECTURE)
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target_link_libraries(dynarmic PRIVATE lagoon::lagoon)
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target_sources(dynarmic PRIVATE
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backend/loongarch64/exclusive_monitor.cpp
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backend/loongarch64/abi.h
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backend/loongarch64/a32_jitstate.cpp
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backend/loongarch64/a32_jitstate.h
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backend/loongarch64/code_block.h
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backend/loongarch64/emit_context.h
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backend/loongarch64/emit_loongarch64.cpp
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backend/loongarch64/emit_loongarch64.h
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backend/loongarch64/emit_loongarch64_a32.cpp
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backend/loongarch64/emit_loongarch64_data_processing.cpp
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backend/loongarch64/a32_address_space.cpp
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backend/loongarch64/a32_address_space.h
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backend/loongarch64/a32_interface.cpp
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backend/loongarch64/a64_interface.cpp
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backend/loongarch64/code_block.h
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backend/loongarch64/exclusive_monitor.cpp
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backend/loongarch64/reg_alloc.cpp
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backend/loongarch64/reg_alloc.h
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backend/loongarch64/stack_layout.h
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backend/loongarch64/lagoon_cpp.h
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common/spin_lock_loongarch64.cpp
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)
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@ -0,0 +1,123 @@
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// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
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// SPDX-License-Identifier: GPL-3.0-or-later
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#include "dynarmic/backend/loongarch64/a32_address_space.h"
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#include "common/assert.h"
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#include "dynarmic/backend/loongarch64/a32_jitstate.h"
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#include "dynarmic/backend/loongarch64/abi.h"
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#include "dynarmic/backend/loongarch64/emit_loongarch64.h"
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#include "dynarmic/frontend/A32/a32_location_descriptor.h"
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#include "dynarmic/frontend/A32/translate/a32_translate.h"
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#include "dynarmic/ir/opt_passes.h"
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namespace Dynarmic::Backend::LoongArch64 {
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A32AddressSpace::A32AddressSpace(const A32::UserConfig& conf)
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: conf(conf)
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, cb(conf.code_cache_size) {
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EmitPrelude();
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}
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void A32AddressSpace::GenerateIR(IR::Block& ir_block, IR::LocationDescriptor descriptor) const {
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A32::Translate(ir_block, A32::LocationDescriptor{descriptor}, conf.callbacks, {conf.arch_version, conf.define_unpredictable_behaviour, conf.hook_hint_instructions});
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Optimization::Optimize(ir_block, conf, {.sha256 = true});
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}
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CodePtr A32AddressSpace::Get(IR::LocationDescriptor descriptor) {
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if (const auto iter = block_entries.find(descriptor.Value()); iter != block_entries.end()) {
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return iter->second;
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}
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return nullptr;
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}
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CodePtr A32AddressSpace::GetOrEmit(IR::LocationDescriptor descriptor) {
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if (CodePtr block_entry = Get(descriptor)) {
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return block_entry;
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}
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IR::Block ir_block{descriptor};
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GenerateIR(ir_block, descriptor);
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const EmittedBlockInfo block_info = Emit(std::move(ir_block));
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block_infos.insert_or_assign(descriptor.Value(), block_info);
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block_entries.insert_or_assign(descriptor.Value(), block_info.entry_point);
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return block_info.entry_point;
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}
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void A32AddressSpace::ClearCache() {
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block_entries.clear();
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block_infos.clear();
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SetCursorPtr(prelude_info.end_of_prelude);
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}
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void A32AddressSpace::EmitPrelude() {
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prelude_info.run_code = GetCursorPtr<PreludeInfo::RunCodeFuncType>();
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// Save all GPRs except sp (r3) and tp (r2)
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la_addi_d(&cb.as, LA_SP, LA_SP, -64 * 8);
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for (u32 i = 1; i < 32; i++) {
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if (i == LA_SP || i == LA_TP)
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continue;
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la_st_d(&cb.as, static_cast<la_gpr_t>(i), LA_SP, static_cast<int32_t>(i * 8));
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}
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// Set up reserved registers and jump to block entry
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la_move(&cb.as, Xstate, LA_A1); // Xstate = state ptr
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la_move(&cb.as, Xhalt, LA_A2); // Xhalt = halt reason ptr
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la_jr(&cb.as, LA_A0); // jump to block_entry
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prelude_info.return_from_run_code = GetCursorPtr<CodePtr>();
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// Restore all GPRs except sp and tp
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for (u32 i = 1; i < 32; i++) {
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if (i == LA_SP || i == LA_TP)
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continue;
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la_ld_d(&cb.as, static_cast<la_gpr_t>(i), LA_SP, static_cast<int32_t>(i * 8));
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}
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la_addi_d(&cb.as, LA_SP, LA_SP, 64 * 8);
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la_ret(&cb.as);
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prelude_info.end_of_prelude = GetCursorPtr<CodePtr>();
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}
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void A32AddressSpace::SetCursorPtr(CodePtr ptr) {
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cb.as.cursor = reinterpret_cast<uint8_t*>(ptr);
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}
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size_t A32AddressSpace::GetRemainingSize() {
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return la_get_remaining_buffer_size(&cb.as);
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}
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EmittedBlockInfo A32AddressSpace::Emit(IR::Block block) {
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if (GetRemainingSize() < 1024 * 1024) {
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ClearCache();
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}
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EmitConfig emit_conf{};
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EmittedBlockInfo block_info = EmitLoongArch64(cb.as, std::move(block), emit_conf);
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Link(block_info);
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return block_info;
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}
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void A32AddressSpace::Link(EmittedBlockInfo& block_info) {
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for (const auto& reloc : block_info.relocations) {
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uint8_t* patch_location = reinterpret_cast<uint8_t*>(block_info.entry_point) + reloc.code_offset;
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switch (reloc.target) {
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case LinkTarget::ReturnFromRunCode: {
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std::ptrdiff_t off = reinterpret_cast<uint8_t*>(prelude_info.return_from_run_code) - patch_location;
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lagoon_assembler_t patch_as;
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la_init_assembler(&patch_as, patch_location, 4);
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la_b(&patch_as, static_cast<int32_t>(off));
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break;
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}
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default:
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ASSERT(false && "Invalid relocation target");
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}
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}
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}
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} // namespace Dynarmic::Backend::LoongArch64
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@ -0,0 +1,68 @@
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// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
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// SPDX-License-Identifier: GPL-3.0-or-later
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#pragma once
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#include "dynarmic/backend/loongarch64/lagoon_cpp.h"
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#include <ankerl/unordered_dense.h>
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#include "dynarmic/backend/loongarch64/code_block.h"
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#include "dynarmic/backend/loongarch64/emit_loongarch64.h"
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#include "dynarmic/interface/A32/config.h"
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#include "dynarmic/interface/halt_reason.h"
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#include "dynarmic/ir/basic_block.h"
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#include "dynarmic/ir/location_descriptor.h"
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namespace Dynarmic::Backend::LoongArch64 {
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struct A32JitState;
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class A32AddressSpace final {
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public:
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explicit A32AddressSpace(const A32::UserConfig& conf);
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void GenerateIR(IR::Block& ir_block, IR::LocationDescriptor descriptor) const;
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CodePtr Get(IR::LocationDescriptor descriptor);
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CodePtr GetOrEmit(IR::LocationDescriptor descriptor);
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void ClearCache();
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private:
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void EmitPrelude();
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template<typename T>
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T GetCursorPtr() {
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return reinterpret_cast<T>(cb.as.cursor);
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}
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template<typename T>
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T GetCursorPtr() const {
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return reinterpret_cast<T>(cb.as.cursor);
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}
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template<typename T>
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T GetMemPtr() const {
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return cb.ptr<T>();
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}
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void SetCursorPtr(CodePtr ptr);
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size_t GetRemainingSize();
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EmittedBlockInfo Emit(IR::Block block);
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void Link(EmittedBlockInfo& block_info);
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const A32::UserConfig conf;
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CodeBlock cb;
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ankerl::unordered_dense::map<u64, CodePtr> block_entries;
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ankerl::unordered_dense::map<u64, EmittedBlockInfo> block_infos;
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public:
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struct PreludeInfo {
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CodePtr end_of_prelude;
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using RunCodeFuncType = HaltReason (*)(CodePtr entry_point, A32JitState* context, volatile u32* halt_reason);
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RunCodeFuncType run_code;
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CodePtr return_from_run_code;
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} prelude_info;
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};
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} // namespace Dynarmic::Backend::LoongArch64
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@ -1,101 +1,134 @@
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// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
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// SPDX-License-Identifier: GPL-3.0-or-later
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#include <array>
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#include <memory>
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#include <string>
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#include <utility>
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#include <mutex>
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#include <boost/icl/interval_set.hpp>
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "dynarmic/backend/loongarch64/a32_address_space.h"
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#include "dynarmic/backend/loongarch64/a32_jitstate.h"
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#include "dynarmic/common/atomic.h"
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#include "dynarmic/frontend/A32/a32_location_descriptor.h"
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#include "dynarmic/interface/A32/a32.h"
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namespace Dynarmic::A32 {
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using namespace Backend::LoongArch64;
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struct Jit::Impl final {
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explicit Impl(UserConfig conf_) : conf(std::move(conf_)) {}
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Impl(Jit* jit_interface, A32::UserConfig conf)
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: jit_interface(jit_interface)
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, conf(conf)
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, current_address_space(conf) {}
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HaltReason Run() {
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UNIMPLEMENTED();
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return halt_reason;
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ASSERT(!jit_interface->is_executing);
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jit_interface->is_executing = true;
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const auto location_descriptor = current_state.GetLocationDescriptor();
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const auto entry_point = current_address_space.GetOrEmit(location_descriptor);
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current_address_space.prelude_info.run_code(entry_point, ¤t_state, &halt_reason);
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HaltReason hr = static_cast<HaltReason>(Atomic::Exchange(&halt_reason, 0));
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jit_interface->is_executing = false;
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return hr;
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}
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HaltReason Step() {
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UNIMPLEMENTED();
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return halt_reason | HaltReason::Step;
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ASSERT(!jit_interface->is_executing);
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jit_interface->is_executing = true;
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const auto location_descriptor = A32::LocationDescriptor{current_state.GetLocationDescriptor()}.SetSingleStepping(true);
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const auto entry_point = current_address_space.GetOrEmit(location_descriptor);
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current_address_space.prelude_info.run_code(entry_point, ¤t_state, &halt_reason);
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HaltReason hr = static_cast<HaltReason>(Atomic::Exchange(&halt_reason, 0));
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jit_interface->is_executing = false;
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return hr;
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}
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void ClearCache() {
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std::unique_lock lock{invalidation_mutex};
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invalidate_entire_cache = true;
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HaltExecution(HaltReason::CacheInvalidation);
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}
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void InvalidateCacheRange(u32, std::size_t) {
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void InvalidateCacheRange(u32 start_address, size_t length) {
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std::unique_lock lock{invalidation_mutex};
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invalid_cache_ranges.add(boost::icl::discrete_interval<u32>::closed(start_address, static_cast<u32>(start_address + length - 1)));
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HaltExecution(HaltReason::CacheInvalidation);
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}
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void Reset() {
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regs = {};
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ext_regs = {};
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cpsr = 0;
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fpscr = 0;
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halt_reason = {};
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current_state = {};
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}
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void HaltExecution(HaltReason hr) {
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halt_reason |= hr;
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Atomic::Or(&halt_reason, static_cast<u32>(hr));
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}
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void ClearHalt(HaltReason hr) {
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halt_reason &= ~hr;
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Atomic::And(&halt_reason, ~static_cast<u32>(hr));
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}
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std::array<u32, 16>& Regs() {
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return regs;
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return current_state.regs;
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}
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const std::array<u32, 16>& Regs() const {
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return regs;
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return current_state.regs;
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}
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std::array<u32, 64>& ExtRegs() {
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return ext_regs;
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return current_state.ext_regs;
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}
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const std::array<u32, 64>& ExtRegs() const {
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return ext_regs;
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return current_state.ext_regs;
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}
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u32 Cpsr() const {
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return cpsr;
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return current_state.Cpsr();
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}
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void SetCpsr(u32 value) {
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cpsr = value;
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current_state.SetCpsr(value);
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}
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u32 Fpscr() const {
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return fpscr;
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return current_state.Fpscr();
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}
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void SetFpscr(u32 value) {
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fpscr = value;
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current_state.SetFpscr(value);
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}
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void ClearExclusiveState() {}
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void ClearExclusiveState() {
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current_state.exclusive_state = false;
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}
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std::string Disassemble() const {
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return {};
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}
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UserConfig conf;
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std::array<u32, 16> regs{};
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std::array<u32, 64> ext_regs{};
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u32 cpsr = 0;
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u32 fpscr = 0;
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HaltReason halt_reason{};
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private:
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Jit* jit_interface;
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A32::UserConfig conf;
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A32JitState current_state{};
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A32AddressSpace current_address_space;
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volatile u32 halt_reason = 0;
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std::mutex invalidation_mutex;
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boost::icl::interval_set<u32> invalid_cache_ranges;
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bool invalidate_entire_cache = false;
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};
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Jit::Jit(UserConfig conf) : impl(std::make_unique<Impl>(std::move(conf))) {}
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Jit::Jit(UserConfig conf)
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: impl(std::make_unique<Impl>(this, conf)) {}
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Jit::~Jit() = default;
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@ -111,7 +144,7 @@ void Jit::ClearCache() {
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impl->ClearCache();
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}
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void Jit::InvalidateCacheRange(u32 start_address, std::size_t length) {
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void Jit::InvalidateCacheRange(u32 start_address, size_t length) {
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impl->InvalidateCacheRange(start_address, length);
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}
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@ -0,0 +1,57 @@
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// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
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// SPDX-License-Identifier: GPL-3.0-or-later
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#include "dynarmic/backend/loongarch64/a32_jitstate.h"
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#include "dynarmic/mcl/bit.hpp"
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#include "common/common_types.h"
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namespace Dynarmic::Backend::LoongArch64 {
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u32 A32JitState::Cpsr() const {
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u32 cpsr = 0;
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cpsr |= cpsr_nzcv;
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cpsr |= cpsr_q;
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cpsr |= mcl::bit::get_bit<31>(cpsr_ge) ? 1 << 19 : 0;
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cpsr |= mcl::bit::get_bit<23>(cpsr_ge) ? 1 << 18 : 0;
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cpsr |= mcl::bit::get_bit<15>(cpsr_ge) ? 1 << 17 : 0;
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cpsr |= mcl::bit::get_bit<7>(cpsr_ge) ? 1 << 16 : 0;
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cpsr |= mcl::bit::get_bit<1>(upper_location_descriptor) ? 1 << 9 : 0;
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cpsr |= mcl::bit::get_bit<0>(upper_location_descriptor) ? 1 << 5 : 0;
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cpsr |= static_cast<u32>(upper_location_descriptor & 0b11111100'00000000);
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cpsr |= static_cast<u32>(upper_location_descriptor & 0b00000011'00000000) << 17;
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cpsr |= cpsr_jaifm;
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return cpsr;
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}
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void A32JitState::SetCpsr(u32 cpsr) {
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cpsr_nzcv = cpsr & 0xF0000000;
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cpsr_q = cpsr & (1 << 27);
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cpsr_ge = 0;
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cpsr_ge |= mcl::bit::get_bit<19>(cpsr) ? 0xFF000000 : 0;
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cpsr_ge |= mcl::bit::get_bit<18>(cpsr) ? 0x00FF0000 : 0;
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cpsr_ge |= mcl::bit::get_bit<17>(cpsr) ? 0x0000FF00 : 0;
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cpsr_ge |= mcl::bit::get_bit<16>(cpsr) ? 0x000000FF : 0;
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upper_location_descriptor &= 0xFFFF0000;
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upper_location_descriptor |= mcl::bit::get_bit<9>(cpsr) ? 2 : 0;
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upper_location_descriptor |= mcl::bit::get_bit<5>(cpsr) ? 1 : 0;
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upper_location_descriptor |= (cpsr >> 0) & 0b11111100'00000000;
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||||
upper_location_descriptor |= (cpsr >> 17) & 0b00000011'00000000;
|
||||
cpsr_jaifm = cpsr & 0x010001DF;
|
||||
}
|
||||
|
||||
constexpr u32 FPCR_MASK = A32::LocationDescriptor::FPSCR_MODE_MASK;
|
||||
constexpr u32 FPSR_MASK = 0x0800009F;
|
||||
|
||||
u32 A32JitState::Fpscr() const {
|
||||
return (upper_location_descriptor & FPCR_MASK) | fpsr | fpsr_nzcv;
|
||||
}
|
||||
|
||||
void A32JitState::SetFpscr(u32 fpscr) {
|
||||
fpsr = fpscr & FPSR_MASK;
|
||||
fpsr_nzcv = fpscr & 0xF0000000;
|
||||
upper_location_descriptor = (upper_location_descriptor & 0x0000ffff) | (fpscr & FPCR_MASK);
|
||||
}
|
||||
|
||||
} // namespace Dynarmic::Backend::LoongArch64
|
||||
43
src/dynarmic/src/dynarmic/backend/loongarch64/a32_jitstate.h
Normal file
43
src/dynarmic/src/dynarmic/backend/loongarch64/a32_jitstate.h
Normal file
@ -0,0 +1,43 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
|
||||
// SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <array>
|
||||
|
||||
#include "common/common_types.h"
|
||||
|
||||
#include "dynarmic/frontend/A32/a32_location_descriptor.h"
|
||||
#include "dynarmic/ir/location_descriptor.h"
|
||||
|
||||
namespace Dynarmic::Backend::LoongArch64 {
|
||||
|
||||
struct A32JitState {
|
||||
u32 cpsr_nzcv = 0;
|
||||
u32 cpsr_q = 0;
|
||||
u32 cpsr_jaifm = 0;
|
||||
u32 cpsr_ge = 0;
|
||||
|
||||
u32 fpsr = 0;
|
||||
u32 fpsr_nzcv = 0;
|
||||
|
||||
std::array<u32, 16> regs{};
|
||||
|
||||
u32 upper_location_descriptor;
|
||||
|
||||
alignas(16) std::array<u32, 64> ext_regs{};
|
||||
|
||||
u32 exclusive_state = 0;
|
||||
|
||||
u32 Cpsr() const;
|
||||
void SetCpsr(u32 cpsr);
|
||||
|
||||
u32 Fpscr() const;
|
||||
void SetFpscr(u32 fpscr);
|
||||
|
||||
IR::LocationDescriptor GetLocationDescriptor() const {
|
||||
return IR::LocationDescriptor{regs[15] | (static_cast<u64>(upper_location_descriptor) << 32)};
|
||||
}
|
||||
};
|
||||
|
||||
} // namespace Dynarmic::Backend::LoongArch64
|
||||
39
src/dynarmic/src/dynarmic/backend/loongarch64/abi.h
Normal file
39
src/dynarmic/src/dynarmic/backend/loongarch64/abi.h
Normal file
@ -0,0 +1,39 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
|
||||
// SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <initializer_list>
|
||||
|
||||
#include "dynarmic/backend/loongarch64/lagoon_cpp.h"
|
||||
|
||||
#include "common/common_types.h"
|
||||
|
||||
namespace Dynarmic::Backend::LoongArch64 {
|
||||
|
||||
// Reserved registers used by the dynarmic JIT
|
||||
// Xstate (s0/r23): pointer to JIT CPU state, callee-saved
|
||||
// Xhalt (s1/r24): halt reason pointer, callee-saved
|
||||
// Xscratch0 (t7/r19): scratch register (caller-saved)
|
||||
// Xscratch1 (t8/r20): scratch register (caller-saved)
|
||||
constexpr la_gpr_t Xstate = LA_S0; // r23
|
||||
constexpr la_gpr_t Xhalt = LA_S1; // r24
|
||||
constexpr la_gpr_t Xscratch0 = LA_T7; // r19
|
||||
constexpr la_gpr_t Xscratch1 = LA_T8; // r20
|
||||
|
||||
// GPR allocation order: callee-saved (s2-s8) first, then temps, then args
|
||||
constexpr std::initializer_list<u32> GPR_ORDER{
|
||||
25, 26, 27, 28, 29, 30, 31, // s2-s8 (r25-r31)
|
||||
12, 13, 14, 15, 16, 17, 18, // t0-t6 (r12-r18)
|
||||
4, 5, 6, 7, 8, 9, 10, 11 // a0-a7 (r4-r11)
|
||||
};
|
||||
|
||||
// FPR allocation order: callee-saved (fs0-fs7) first, then ft, then fa
|
||||
constexpr std::initializer_list<u32> FPR_ORDER{
|
||||
24, 25, 26, 27, 28, 29, 30, 31, // fs0-fs7 (f24-f31)
|
||||
8, 9, 10, 11, 12, 13, 14, 15, // ft0-ft7 (f8-f15)
|
||||
16, 17, 18, 19, 20, 21, 22, 23, // ft8-ft15 (f16-f23)
|
||||
0, 1, 2, 3, 4, 5, 6, 7 // fa0-fa7 (f0-f7)
|
||||
};
|
||||
|
||||
} // namespace Dynarmic::Backend::LoongArch64
|
||||
@ -4,20 +4,44 @@
|
||||
#pragma once
|
||||
|
||||
#include <cstdint>
|
||||
#include <new>
|
||||
#include <type_traits>
|
||||
|
||||
#include <sys/mman.h>
|
||||
#include "dynarmic/backend/loongarch64/lagoon_cpp.h"
|
||||
|
||||
#include "common/assert.h"
|
||||
#include "common/common_types.h"
|
||||
|
||||
namespace Dynarmic::Backend::LoongArch64 {
|
||||
|
||||
class CodeBlock {
|
||||
public:
|
||||
explicit CodeBlock(std::size_t size) noexcept
|
||||
: memsize(size) {
|
||||
mem = static_cast<u8*>(mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE, -1, 0));
|
||||
ASSERT(mem != MAP_FAILED);
|
||||
la_init_assembler(&as, mem, size);
|
||||
}
|
||||
|
||||
~CodeBlock() noexcept {
|
||||
if (mem == nullptr) {
|
||||
return;
|
||||
}
|
||||
munmap(mem, memsize);
|
||||
}
|
||||
|
||||
template<typename T>
|
||||
T ptr() const noexcept {
|
||||
static_assert(std::is_pointer_v<T> || std::is_same_v<T, std::uintptr_t> || std::is_same_v<T, std::intptr_t>);
|
||||
return reinterpret_cast<T>(mem);
|
||||
}
|
||||
|
||||
lagoon_assembler_t as{};
|
||||
|
||||
private:
|
||||
u8* mem = nullptr;
|
||||
size_t memsize = 0;
|
||||
};
|
||||
|
||||
} // namespace Dynarmic::Backend::LoongArch64
|
||||
|
||||
24
src/dynarmic/src/dynarmic/backend/loongarch64/emit_context.h
Normal file
24
src/dynarmic/src/dynarmic/backend/loongarch64/emit_context.h
Normal file
@ -0,0 +1,24 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
|
||||
// SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "dynarmic/backend/loongarch64/emit_loongarch64.h"
|
||||
#include "dynarmic/backend/loongarch64/reg_alloc.h"
|
||||
|
||||
namespace Dynarmic::IR {
|
||||
class Block;
|
||||
} // namespace Dynarmic::IR
|
||||
|
||||
namespace Dynarmic::Backend::LoongArch64 {
|
||||
|
||||
struct EmitConfig;
|
||||
|
||||
struct EmitContext {
|
||||
IR::Block& block;
|
||||
RegAlloc& reg_alloc;
|
||||
const EmitConfig& emit_conf;
|
||||
EmittedBlockInfo& ebi;
|
||||
};
|
||||
|
||||
} // namespace Dynarmic::Backend::LoongArch64
|
||||
@ -0,0 +1,113 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
|
||||
// SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
#include "dynarmic/backend/loongarch64/emit_loongarch64.h"
|
||||
|
||||
#include "dynarmic/backend/loongarch64/a32_jitstate.h"
|
||||
#include "dynarmic/backend/loongarch64/abi.h"
|
||||
#include "dynarmic/backend/loongarch64/emit_context.h"
|
||||
#include "dynarmic/backend/loongarch64/reg_alloc.h"
|
||||
#include "dynarmic/ir/basic_block.h"
|
||||
#include "dynarmic/ir/microinstruction.h"
|
||||
#include "dynarmic/ir/opcodes.h"
|
||||
|
||||
namespace Dynarmic::Backend::LoongArch64 {
|
||||
|
||||
template<IR::Opcode op>
|
||||
void EmitIR(lagoon_assembler_t&, EmitContext&, IR::Inst*) {
|
||||
ASSERT(false && "Unimplemented opcode");
|
||||
}
|
||||
|
||||
template<>
|
||||
void EmitIR<IR::Opcode::Void>(lagoon_assembler_t&, EmitContext&, IR::Inst*) {}
|
||||
|
||||
template<>
|
||||
void EmitIR<IR::Opcode::A32GetRegister>(lagoon_assembler_t&, EmitContext& ctx, IR::Inst* inst);
|
||||
|
||||
template<>
|
||||
void EmitIR<IR::Opcode::A32SetRegister>(lagoon_assembler_t&, EmitContext& ctx, IR::Inst* inst);
|
||||
|
||||
template<>
|
||||
void EmitIR<IR::Opcode::A32SetCpsrNZC>(lagoon_assembler_t&, EmitContext& ctx, IR::Inst* inst);
|
||||
|
||||
template<>
|
||||
void EmitIR<IR::Opcode::LogicalShiftLeft32>(lagoon_assembler_t&, EmitContext& ctx, IR::Inst* inst);
|
||||
|
||||
template<>
|
||||
void EmitIR<IR::Opcode::GetCarryFromOp>(lagoon_assembler_t&, EmitContext& ctx, IR::Inst* inst) {
|
||||
ASSERT(ctx.reg_alloc.IsValueLive(inst));
|
||||
}
|
||||
|
||||
template<>
|
||||
void EmitIR<IR::Opcode::GetNZFromOp>(lagoon_assembler_t& as, EmitContext& ctx, IR::Inst* inst) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
auto Xvalue = ctx.reg_alloc.ReadX(args[0]);
|
||||
auto Xnz = ctx.reg_alloc.WriteX(inst);
|
||||
RegAlloc::Realize(Xvalue, Xnz);
|
||||
|
||||
// Z flag (bit 30): set if value == 0
|
||||
la_sltui(&as, Xnz->index, Xvalue->index, 1);
|
||||
la_slli_d(&as, Xnz->index, Xnz->index, 30);
|
||||
// N flag (bit 31): set if value < 0 (signed)
|
||||
la_slt(&as, Xscratch0, Xvalue->index, LA_ZERO);
|
||||
la_slli_d(&as, Xscratch0, Xscratch0, 31);
|
||||
la_or(&as, Xnz->index, Xnz->index, Xscratch0);
|
||||
}
|
||||
|
||||
EmittedBlockInfo EmitLoongArch64(lagoon_assembler_t& as, IR::Block block, const EmitConfig& emit_conf) {
|
||||
EmittedBlockInfo ebi;
|
||||
|
||||
RegAlloc reg_alloc{as, std::vector<u32>(GPR_ORDER), std::vector<u32>(FPR_ORDER)};
|
||||
EmitContext ctx{block, reg_alloc, emit_conf, ebi};
|
||||
|
||||
ebi.entry_point = reinterpret_cast<CodePtr>(as.cursor);
|
||||
|
||||
for (auto iter = block.instructions.begin(); iter != block.instructions.end(); ++iter) {
|
||||
IR::Inst* inst = &*iter;
|
||||
|
||||
switch (inst->GetOpcode()) {
|
||||
#define OPCODE(name, type, ...) \
|
||||
case IR::Opcode::name: \
|
||||
EmitIR<IR::Opcode::name>(as, ctx, inst); \
|
||||
break;
|
||||
#define A32OPC(name, type, ...) \
|
||||
case IR::Opcode::A32##name: \
|
||||
EmitIR<IR::Opcode::A32##name>(as, ctx, inst); \
|
||||
break;
|
||||
#define A64OPC(name, type, ...) \
|
||||
case IR::Opcode::A64##name: \
|
||||
EmitIR<IR::Opcode::A64##name>(as, ctx, inst); \
|
||||
break;
|
||||
#include "dynarmic/ir/opcodes.inc"
|
||||
#undef OPCODE
|
||||
#undef A32OPC
|
||||
#undef A64OPC
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
reg_alloc.UpdateAllUses();
|
||||
}
|
||||
|
||||
reg_alloc.UpdateAllUses();
|
||||
reg_alloc.AssertNoMoreUses();
|
||||
|
||||
// TODO: Emit Terminal
|
||||
const auto term = block.GetTerminal();
|
||||
const IR::Term::LinkBlock* link_block_term = boost::get<IR::Term::LinkBlock>(&term);
|
||||
ASSERT(link_block_term);
|
||||
la_load_immediate64(&as, Xscratch0, link_block_term->next.Value());
|
||||
la_st_w(&as, Xscratch0, Xstate, static_cast<int32_t>(offsetof(A32JitState, regs) + sizeof(u32) * 15));
|
||||
|
||||
ebi.relocations.push_back(Relocation{
|
||||
reinterpret_cast<CodePtr>(as.cursor) - ebi.entry_point,
|
||||
LinkTarget::ReturnFromRunCode
|
||||
});
|
||||
la_nop(&as);
|
||||
|
||||
ebi.size = reinterpret_cast<CodePtr>(as.cursor) - ebi.entry_point;
|
||||
return ebi;
|
||||
}
|
||||
|
||||
} // namespace Dynarmic::Backend::LoongArch64
|
||||
@ -0,0 +1,55 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
|
||||
// SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <array>
|
||||
#include <cstddef>
|
||||
#include <vector>
|
||||
|
||||
#include "dynarmic/backend/loongarch64/lagoon_cpp.h"
|
||||
|
||||
#include "common/common_types.h"
|
||||
|
||||
namespace Dynarmic::IR {
|
||||
class Block;
|
||||
class Inst;
|
||||
class LocationDescriptor;
|
||||
enum class Cond;
|
||||
enum class Opcode;
|
||||
} // namespace Dynarmic::IR
|
||||
|
||||
namespace Dynarmic::A32 {
|
||||
class Coprocessor;
|
||||
} // namespace Dynarmic::A32
|
||||
|
||||
namespace Dynarmic::Backend::LoongArch64 {
|
||||
|
||||
using CodePtr = std::byte*;
|
||||
|
||||
enum class LinkTarget {
|
||||
ReturnFromRunCode,
|
||||
};
|
||||
|
||||
struct Relocation {
|
||||
std::ptrdiff_t code_offset;
|
||||
LinkTarget target;
|
||||
};
|
||||
|
||||
struct EmittedBlockInfo {
|
||||
std::vector<Relocation> relocations;
|
||||
CodePtr entry_point;
|
||||
size_t size;
|
||||
size_t cycle_count;
|
||||
};
|
||||
|
||||
struct EmitConfig {};
|
||||
|
||||
struct EmitContext;
|
||||
|
||||
template<IR::Opcode op>
|
||||
void EmitIR(lagoon_assembler_t& as, EmitContext& ctx, IR::Inst* inst);
|
||||
|
||||
EmittedBlockInfo EmitLoongArch64(lagoon_assembler_t& as, IR::Block block, const EmitConfig& emit_conf);
|
||||
|
||||
} // namespace Dynarmic::Backend::LoongArch64
|
||||
@ -0,0 +1,59 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
|
||||
// SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
#include "dynarmic/backend/loongarch64/lagoon_cpp.h"
|
||||
|
||||
#include "dynarmic/backend/loongarch64/a32_jitstate.h"
|
||||
#include "dynarmic/backend/loongarch64/abi.h"
|
||||
#include "dynarmic/backend/loongarch64/emit_context.h"
|
||||
#include "dynarmic/backend/loongarch64/emit_loongarch64.h"
|
||||
#include "dynarmic/backend/loongarch64/reg_alloc.h"
|
||||
#include "dynarmic/ir/basic_block.h"
|
||||
#include "dynarmic/ir/microinstruction.h"
|
||||
#include "dynarmic/ir/opcodes.h"
|
||||
|
||||
namespace Dynarmic::Backend::LoongArch64 {
|
||||
|
||||
template<>
|
||||
void EmitIR<IR::Opcode::A32GetRegister>(lagoon_assembler_t& as, EmitContext& ctx, IR::Inst* inst) {
|
||||
const A32::Reg reg = inst->GetArg(0).GetA32RegRef();
|
||||
|
||||
auto Xresult = ctx.reg_alloc.WriteX(inst);
|
||||
RegAlloc::Realize(Xresult);
|
||||
|
||||
la_ld_wu(&as, Xresult->index, Xstate,
|
||||
static_cast<int32_t>(offsetof(A32JitState, regs) + sizeof(u32) * static_cast<size_t>(reg)));
|
||||
}
|
||||
|
||||
template<>
|
||||
void EmitIR<IR::Opcode::A32SetRegister>(lagoon_assembler_t& as, EmitContext& ctx, IR::Inst* inst) {
|
||||
const A32::Reg reg = inst->GetArg(0).GetA32RegRef();
|
||||
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
auto Xvalue = ctx.reg_alloc.ReadX(args[1]);
|
||||
RegAlloc::Realize(Xvalue);
|
||||
|
||||
la_st_w(&as, Xvalue->index, Xstate,
|
||||
static_cast<int32_t>(offsetof(A32JitState, regs) + sizeof(u32) * static_cast<size_t>(reg)));
|
||||
}
|
||||
|
||||
template<>
|
||||
void EmitIR<IR::Opcode::A32SetCpsrNZC>(lagoon_assembler_t& as, EmitContext& ctx, IR::Inst* inst) {
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
|
||||
ASSERT(!args[0].IsImmediate() && !args[1].IsImmediate());
|
||||
|
||||
auto Xnz = ctx.reg_alloc.ReadX(args[0]);
|
||||
auto Xc = ctx.reg_alloc.ReadX(args[1]);
|
||||
RegAlloc::Realize(Xnz, Xc);
|
||||
|
||||
la_ld_wu(&as, Xscratch0, Xstate, static_cast<int32_t>(offsetof(A32JitState, cpsr_nzcv)));
|
||||
la_load_immediate64(&as, Xscratch1, 0x10000000);
|
||||
la_and(&as, Xscratch0, Xscratch0, Xscratch1);
|
||||
la_or(&as, Xscratch0, Xscratch0, Xnz->index);
|
||||
la_slli_w(&as, Xscratch1, Xc->index, 29);
|
||||
la_or(&as, Xscratch0, Xscratch0, Xscratch1);
|
||||
la_st_w(&as, Xscratch0, Xstate, static_cast<int32_t>(offsetof(A32JitState, cpsr_nzcv)));
|
||||
}
|
||||
|
||||
} // namespace Dynarmic::Backend::LoongArch64
|
||||
@ -0,0 +1,52 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
|
||||
// SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
#include "dynarmic/backend/loongarch64/lagoon_cpp.h"
|
||||
|
||||
#include "dynarmic/backend/loongarch64/abi.h"
|
||||
#include "dynarmic/backend/loongarch64/emit_context.h"
|
||||
#include "dynarmic/backend/loongarch64/emit_loongarch64.h"
|
||||
#include "dynarmic/backend/loongarch64/reg_alloc.h"
|
||||
#include "dynarmic/ir/basic_block.h"
|
||||
#include "dynarmic/ir/microinstruction.h"
|
||||
#include "dynarmic/ir/opcodes.h"
|
||||
|
||||
namespace Dynarmic::Backend::LoongArch64 {
|
||||
|
||||
template<>
|
||||
void EmitIR<IR::Opcode::LogicalShiftLeft32>(lagoon_assembler_t& as, EmitContext& ctx, IR::Inst* inst) {
|
||||
const auto carry_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetCarryFromOp);
|
||||
|
||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||
auto& operand_arg = args[0];
|
||||
auto& shift_arg = args[1];
|
||||
auto& carry_arg = args[2];
|
||||
|
||||
ASSERT(carry_inst != nullptr);
|
||||
ASSERT(shift_arg.IsImmediate());
|
||||
|
||||
auto Xresult = ctx.reg_alloc.WriteX(inst);
|
||||
auto Xcarry_out = ctx.reg_alloc.WriteX(carry_inst);
|
||||
auto Xoperand = ctx.reg_alloc.ReadX(operand_arg);
|
||||
auto Xcarry_in = ctx.reg_alloc.ReadX(carry_arg);
|
||||
RegAlloc::Realize(Xresult, Xcarry_out, Xoperand, Xcarry_in);
|
||||
|
||||
const u8 shift = shift_arg.GetImmediateU8();
|
||||
|
||||
if (shift == 0) {
|
||||
la_addi_w(&as, Xresult->index, Xoperand->index, 0);
|
||||
la_addi_w(&as, Xcarry_out->index, Xcarry_in->index, 0);
|
||||
} else if (shift < 32) {
|
||||
la_srli_w(&as, Xcarry_out->index, Xoperand->index, 32 - shift);
|
||||
la_andi(&as, Xcarry_out->index, Xcarry_out->index, 1);
|
||||
la_slli_w(&as, Xresult->index, Xoperand->index, shift);
|
||||
} else if (shift > 32) {
|
||||
la_move(&as, Xresult->index, LA_ZERO);
|
||||
la_move(&as, Xcarry_out->index, LA_ZERO);
|
||||
} else {
|
||||
la_andi(&as, Xcarry_out->index, Xoperand->index, 1);
|
||||
la_move(&as, Xresult->index, LA_ZERO);
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace Dynarmic::Backend::LoongArch64
|
||||
@ -0,0 +1,8 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
|
||||
// SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
extern "C" {
|
||||
#include <lagoon.h>
|
||||
}
|
||||
364
src/dynarmic/src/dynarmic/backend/loongarch64/reg_alloc.cpp
Normal file
364
src/dynarmic/src/dynarmic/backend/loongarch64/reg_alloc.cpp
Normal file
@ -0,0 +1,364 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
|
||||
// SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
#include "dynarmic/backend/loongarch64/reg_alloc.h"
|
||||
|
||||
#include <algorithm>
|
||||
#include <array>
|
||||
#include <limits>
|
||||
|
||||
#include "dynarmic/backend/loongarch64/lagoon_cpp.h"
|
||||
|
||||
#include "common/assert.h"
|
||||
#include "common/common_types.h"
|
||||
|
||||
#include "dynarmic/common/always_false.h"
|
||||
|
||||
namespace Dynarmic::Backend::LoongArch64 {
|
||||
|
||||
constexpr size_t spill_offset = offsetof(StackLayout, spill);
|
||||
constexpr size_t spill_slot_size = sizeof(decltype(StackLayout::spill)::value_type);
|
||||
|
||||
static bool IsValuelessType(IR::Type type) {
|
||||
switch (type) {
|
||||
case IR::Type::Table:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
IR::Type Argument::GetType() const {
|
||||
return value.GetType();
|
||||
}
|
||||
|
||||
bool Argument::IsImmediate() const {
|
||||
return value.IsImmediate();
|
||||
}
|
||||
|
||||
bool Argument::GetImmediateU1() const {
|
||||
return value.GetU1();
|
||||
}
|
||||
|
||||
u8 Argument::GetImmediateU8() const {
|
||||
const u64 imm = value.GetImmediateAsU64();
|
||||
ASSERT(imm < 0x100);
|
||||
return u8(imm);
|
||||
}
|
||||
|
||||
u16 Argument::GetImmediateU16() const {
|
||||
const u64 imm = value.GetImmediateAsU64();
|
||||
ASSERT(imm < 0x10000);
|
||||
return u16(imm);
|
||||
}
|
||||
|
||||
u32 Argument::GetImmediateU32() const {
|
||||
const u64 imm = value.GetImmediateAsU64();
|
||||
ASSERT(imm < 0x100000000);
|
||||
return u32(imm);
|
||||
}
|
||||
|
||||
u64 Argument::GetImmediateU64() const {
|
||||
return value.GetImmediateAsU64();
|
||||
}
|
||||
|
||||
IR::Cond Argument::GetImmediateCond() const {
|
||||
ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
|
||||
return value.GetCond();
|
||||
}
|
||||
|
||||
IR::AccType Argument::GetImmediateAccType() const {
|
||||
ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
|
||||
return value.GetAccType();
|
||||
}
|
||||
|
||||
bool HostLocInfo::Contains(const IR::Inst* value) const {
|
||||
return std::find(values.begin(), values.end(), value) != values.end();
|
||||
}
|
||||
|
||||
void HostLocInfo::SetupScratchLocation() {
|
||||
ASSERT(IsCompletelyEmpty());
|
||||
locked = 1;
|
||||
realized = true;
|
||||
}
|
||||
|
||||
bool HostLocInfo::IsCompletelyEmpty() const {
|
||||
return values.empty() && !locked && !accumulated_uses && !expected_uses && !uses_this_inst && !realized;
|
||||
}
|
||||
|
||||
void HostLocInfo::UpdateUses() {
|
||||
accumulated_uses += uses_this_inst;
|
||||
uses_this_inst = 0;
|
||||
|
||||
if (accumulated_uses == expected_uses) {
|
||||
values.clear();
|
||||
accumulated_uses = 0;
|
||||
expected_uses = 0;
|
||||
}
|
||||
}
|
||||
|
||||
RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) {
|
||||
ArgumentInfo ret = {Argument{}, Argument{}, Argument{}, Argument{}};
|
||||
for (size_t i = 0; i < inst->NumArgs(); i++) {
|
||||
const IR::Value arg = inst->GetArg(i);
|
||||
ret[i].value = arg;
|
||||
if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
|
||||
ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
|
||||
ValueInfo(arg.GetInst()).uses_this_inst++;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool RegAlloc::IsValueLive(IR::Inst* inst) const {
|
||||
return !!ValueLocation(inst);
|
||||
}
|
||||
|
||||
void RegAlloc::UpdateAllUses() {
|
||||
for (auto& info : hostloc_info) {
|
||||
info.UpdateUses();
|
||||
}
|
||||
}
|
||||
|
||||
void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) {
|
||||
ASSERT(!ValueLocation(inst));
|
||||
|
||||
if (arg.value.IsImmediate()) {
|
||||
inst->ReplaceUsesWith(arg.value);
|
||||
return;
|
||||
}
|
||||
|
||||
auto& info = ValueInfo(arg.value.GetInst());
|
||||
info.values.emplace_back(inst);
|
||||
info.expected_uses += inst->UseCount();
|
||||
}
|
||||
|
||||
void RegAlloc::AssertNoMoreUses() const {
|
||||
// TODO: Re-enable this assert once all register allocation issues are fixed
|
||||
// const auto is_empty = [](const auto& i) { return i.IsCompletelyEmpty(); };
|
||||
// ASSERT(std::all_of(hostloc_info.begin(), hostloc_info.end(), is_empty));
|
||||
}
|
||||
|
||||
template<HostLoc::Kind kind>
|
||||
u32 RegAlloc::GenerateImmediate(const IR::Value& value) {
|
||||
if constexpr (kind == HostLoc::Kind::Gpr) {
|
||||
const u32 new_location_index = AllocateRegister(gpr_order, GprOffset);
|
||||
SpillGpr(new_location_index);
|
||||
hostloc_info[GprOffset + new_location_index].SetupScratchLocation();
|
||||
|
||||
la_load_immediate64(&as, static_cast<la_gpr_t>(new_location_index),
|
||||
static_cast<int64_t>(value.GetImmediateAsU64()));
|
||||
|
||||
return new_location_index;
|
||||
} else if constexpr (kind == HostLoc::Kind::Fpr) {
|
||||
ASSERT(false && "Unimplemented instruction");
|
||||
} else {
|
||||
UNREACHABLE();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
template<HostLoc::Kind required_kind>
|
||||
u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
|
||||
if (value.IsImmediate()) {
|
||||
return GenerateImmediate<required_kind>(value);
|
||||
}
|
||||
|
||||
const auto current_location = ValueLocation(value.GetInst());
|
||||
ASSERT(current_location);
|
||||
|
||||
if (current_location->kind == required_kind) {
|
||||
ValueInfo(*current_location).realized = true;
|
||||
return current_location->index;
|
||||
}
|
||||
|
||||
ASSERT(!ValueInfo(*current_location).realized);
|
||||
ASSERT(!ValueInfo(*current_location).locked);
|
||||
|
||||
if constexpr (required_kind == HostLoc::Kind::Gpr) {
|
||||
const u32 new_location_index = AllocateRegister(gpr_order, GprOffset);
|
||||
SpillGpr(new_location_index);
|
||||
|
||||
switch (current_location->kind) {
|
||||
case HostLoc::Kind::Gpr:
|
||||
UNREACHABLE();
|
||||
case HostLoc::Kind::Fpr:
|
||||
la_movfr2gr_d(&as, static_cast<la_gpr_t>(new_location_index),
|
||||
static_cast<la_fpr_t>(current_location->index));
|
||||
break;
|
||||
case HostLoc::Kind::Spill:
|
||||
la_ld_d(&as, static_cast<la_gpr_t>(new_location_index), LA_SP,
|
||||
static_cast<int32_t>(spill_offset + current_location->index * spill_slot_size));
|
||||
break;
|
||||
}
|
||||
|
||||
hostloc_info[GprOffset + new_location_index] = std::exchange(ValueInfo(*current_location), {});
|
||||
hostloc_info[GprOffset + new_location_index].realized = true;
|
||||
return new_location_index;
|
||||
} else if constexpr (required_kind == HostLoc::Kind::Fpr) {
|
||||
const u32 new_location_index = AllocateRegister(fpr_order, FprOffset);
|
||||
SpillFpr(new_location_index);
|
||||
|
||||
switch (current_location->kind) {
|
||||
case HostLoc::Kind::Gpr:
|
||||
la_movgr2fr_d(&as, static_cast<la_fpr_t>(new_location_index),
|
||||
static_cast<la_gpr_t>(current_location->index));
|
||||
break;
|
||||
case HostLoc::Kind::Fpr:
|
||||
UNREACHABLE();
|
||||
case HostLoc::Kind::Spill:
|
||||
la_fld_d(&as, static_cast<la_fpr_t>(new_location_index), LA_SP,
|
||||
static_cast<int32_t>(spill_offset + current_location->index * spill_slot_size));
|
||||
break;
|
||||
}
|
||||
|
||||
hostloc_info[FprOffset + new_location_index] = std::exchange(ValueInfo(*current_location), {});
|
||||
hostloc_info[FprOffset + new_location_index].realized = true;
|
||||
return new_location_index;
|
||||
} else {
|
||||
UNREACHABLE();
|
||||
}
|
||||
}
|
||||
|
||||
u32 RegAlloc::RealizeWriteImpl(const IR::Inst* value, HostLoc::Kind required_kind) {
|
||||
if (value == nullptr) {
|
||||
// Scratch register allocation
|
||||
if (required_kind == HostLoc::Kind::Gpr) {
|
||||
const u32 idx = AllocateRegister(gpr_order, GprOffset);
|
||||
SpillGpr(idx);
|
||||
hostloc_info[GprOffset + idx].SetupScratchLocation();
|
||||
return idx;
|
||||
} else if (required_kind == HostLoc::Kind::Fpr) {
|
||||
const u32 idx = AllocateRegister(fpr_order, FprOffset);
|
||||
SpillFpr(idx);
|
||||
hostloc_info[FprOffset + idx].SetupScratchLocation();
|
||||
return idx;
|
||||
}
|
||||
}
|
||||
|
||||
ASSERT(!ValueLocation(value));
|
||||
|
||||
const auto setup_location = [&](HostLocInfo& info) {
|
||||
info = {};
|
||||
info.values.emplace_back(value);
|
||||
info.locked = true;
|
||||
info.realized = true;
|
||||
info.expected_uses = value->UseCount();
|
||||
};
|
||||
|
||||
if (required_kind == HostLoc::Kind::Gpr) {
|
||||
const u32 new_location_index = AllocateRegister(gpr_order, GprOffset);
|
||||
SpillGpr(new_location_index);
|
||||
setup_location(hostloc_info[GprOffset + new_location_index]);
|
||||
return new_location_index;
|
||||
} else if (required_kind == HostLoc::Kind::Fpr) {
|
||||
const u32 new_location_index = AllocateRegister(fpr_order, FprOffset);
|
||||
SpillFpr(new_location_index);
|
||||
setup_location(hostloc_info[FprOffset + new_location_index]);
|
||||
return new_location_index;
|
||||
} else {
|
||||
UNREACHABLE();
|
||||
}
|
||||
}
|
||||
|
||||
template u32 RegAlloc::RealizeReadImpl<HostLoc::Kind::Gpr>(const IR::Value& value);
|
||||
template u32 RegAlloc::RealizeReadImpl<HostLoc::Kind::Fpr>(const IR::Value& value);
|
||||
|
||||
u32 RegAlloc::AllocateRegister(const std::vector<u32>& order, size_t base_offset) {
|
||||
const auto empty = std::find_if(order.begin(), order.end(), [&](u32 i) {
|
||||
auto& info = hostloc_info[base_offset + i];
|
||||
return info.values.empty() && !info.locked;
|
||||
});
|
||||
if (empty != order.end()) {
|
||||
return *empty;
|
||||
}
|
||||
|
||||
std::vector<u32> candidates;
|
||||
std::copy_if(order.begin(), order.end(), std::back_inserter(candidates), [&](u32 i) {
|
||||
return !hostloc_info[base_offset + i].locked;
|
||||
});
|
||||
ASSERT(!candidates.empty());
|
||||
|
||||
u32 best = candidates[0];
|
||||
size_t min_lru = hostloc_info[base_offset + best].lru_counter;
|
||||
for (size_t i = 1; i < candidates.size(); ++i) {
|
||||
auto& info = hostloc_info[base_offset + candidates[i]];
|
||||
if (info.lru_counter < min_lru) {
|
||||
min_lru = info.lru_counter;
|
||||
best = candidates[i];
|
||||
}
|
||||
}
|
||||
hostloc_info[base_offset + best].lru_counter++;
|
||||
return best;
|
||||
}
|
||||
|
||||
void RegAlloc::SpillGpr(u32 index) {
|
||||
auto& gpr_info = hostloc_info[GprOffset + index];
|
||||
ASSERT(!gpr_info.locked && !gpr_info.realized);
|
||||
if (gpr_info.values.empty()) {
|
||||
return;
|
||||
}
|
||||
const u32 new_location_index = FindFreeSpill();
|
||||
la_st_d(&as, static_cast<la_gpr_t>(index), LA_SP,
|
||||
static_cast<int32_t>(spill_offset + new_location_index * spill_slot_size));
|
||||
hostloc_info[SpillOffset + new_location_index] = std::exchange(gpr_info, {});
|
||||
}
|
||||
|
||||
void RegAlloc::SpillFpr(u32 index) {
|
||||
auto& fpr_info = hostloc_info[FprOffset + index];
|
||||
ASSERT(!fpr_info.locked && !fpr_info.realized);
|
||||
if (fpr_info.values.empty()) {
|
||||
return;
|
||||
}
|
||||
const u32 new_location_index = FindFreeSpill();
|
||||
la_fst_d(&as, static_cast<la_fpr_t>(index), LA_SP,
|
||||
static_cast<int32_t>(spill_offset + new_location_index * spill_slot_size));
|
||||
hostloc_info[SpillOffset + new_location_index] = std::exchange(fpr_info, {});
|
||||
}
|
||||
|
||||
u32 RegAlloc::FindFreeSpill() const {
|
||||
for (size_t i = 0; i < SpillCount; ++i) {
|
||||
if (hostloc_info[SpillOffset + i].values.empty()) {
|
||||
return static_cast<u32>(i);
|
||||
}
|
||||
}
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
std::optional<HostLoc> RegAlloc::ValueLocation(const IR::Inst* value) const {
|
||||
for (size_t i = 0; i < hostloc_info.size(); ++i) {
|
||||
if (hostloc_info[i].Contains(value)) {
|
||||
if (i < GprCount) {
|
||||
return HostLoc{HostLoc::Kind::Gpr, static_cast<u32>(i)};
|
||||
} else if (i < GprCount + FprCount) {
|
||||
return HostLoc{HostLoc::Kind::Fpr, static_cast<u32>(i - GprCount)};
|
||||
} else {
|
||||
return HostLoc{HostLoc::Kind::Spill, static_cast<u32>(i - GprCount - FprCount)};
|
||||
}
|
||||
}
|
||||
}
|
||||
return std::nullopt;
|
||||
}
|
||||
|
||||
HostLocInfo& RegAlloc::ValueInfo(HostLoc host_loc) {
|
||||
switch (host_loc.kind) {
|
||||
case HostLoc::Kind::Gpr:
|
||||
return hostloc_info[GprOffset + host_loc.index];
|
||||
case HostLoc::Kind::Fpr:
|
||||
return hostloc_info[FprOffset + host_loc.index];
|
||||
case HostLoc::Kind::Spill:
|
||||
return hostloc_info[SpillOffset + host_loc.index];
|
||||
}
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
|
||||
for (auto& info : hostloc_info) {
|
||||
if (info.Contains(value)) {
|
||||
return info;
|
||||
}
|
||||
}
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
} // namespace Dynarmic::Backend::LoongArch64
|
||||
232
src/dynarmic/src/dynarmic/backend/loongarch64/reg_alloc.h
Normal file
232
src/dynarmic/src/dynarmic/backend/loongarch64/reg_alloc.h
Normal file
@ -0,0 +1,232 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
|
||||
// SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <array>
|
||||
#include <optional>
|
||||
#include <utility>
|
||||
#include <vector>
|
||||
|
||||
#include "dynarmic/backend/loongarch64/lagoon_cpp.h"
|
||||
#include <ankerl/unordered_dense.h>
|
||||
|
||||
#include "common/assert.h"
|
||||
#include "common/common_types.h"
|
||||
#include "dynarmic/mcl/is_instance_of_template.hpp"
|
||||
|
||||
#include "dynarmic/backend/loongarch64/stack_layout.h"
|
||||
#include "dynarmic/ir/cond.h"
|
||||
#include "dynarmic/ir/microinstruction.h"
|
||||
#include "dynarmic/ir/value.h"
|
||||
|
||||
namespace Dynarmic::Backend::LoongArch64 {
|
||||
|
||||
class RegAlloc;
|
||||
|
||||
// Wrapper types for LoongArch GPR/FPR (replacing biscuit's register types)
|
||||
struct GPR {
|
||||
la_gpr_t index = LA_ZERO;
|
||||
GPR() = default;
|
||||
explicit GPR(u32 i) : index{static_cast<la_gpr_t>(i)} {}
|
||||
uint32_t Index() const { return static_cast<uint32_t>(index); }
|
||||
};
|
||||
|
||||
struct FPR {
|
||||
la_fpr_t index = LA_F0;
|
||||
FPR() = default;
|
||||
explicit FPR(u32 i) : index{static_cast<la_fpr_t>(i)} {}
|
||||
uint32_t Index() const { return static_cast<uint32_t>(index); }
|
||||
};
|
||||
|
||||
struct VPR {
|
||||
la_vpr_t index;
|
||||
VPR() = default;
|
||||
explicit VPR(u32 i) : index{static_cast<la_vpr_t>(i)} {}
|
||||
uint32_t Index() const { return static_cast<uint32_t>(index); }
|
||||
};
|
||||
|
||||
struct HostLoc {
|
||||
enum class Kind {
|
||||
Gpr,
|
||||
Fpr,
|
||||
Spill,
|
||||
} kind;
|
||||
u32 index;
|
||||
};
|
||||
|
||||
struct Argument {
|
||||
public:
|
||||
using copyable_reference = std::reference_wrapper<Argument>;
|
||||
|
||||
IR::Type GetType() const;
|
||||
bool IsImmediate() const;
|
||||
|
||||
bool GetImmediateU1() const;
|
||||
u8 GetImmediateU8() const;
|
||||
u16 GetImmediateU16() const;
|
||||
u32 GetImmediateU32() const;
|
||||
u64 GetImmediateU64() const;
|
||||
IR::Cond GetImmediateCond() const;
|
||||
IR::AccType GetImmediateAccType() const;
|
||||
|
||||
private:
|
||||
friend class RegAlloc;
|
||||
explicit Argument() {}
|
||||
|
||||
IR::Value value;
|
||||
bool allocated = false;
|
||||
};
|
||||
|
||||
template<typename T>
|
||||
struct RAReg {
|
||||
public:
|
||||
static constexpr HostLoc::Kind kind = std::is_same_v<T, FPR> || std::is_same_v<T, VPR>
|
||||
? HostLoc::Kind::Fpr
|
||||
: HostLoc::Kind::Gpr;
|
||||
|
||||
operator T() const { return *reg; }
|
||||
|
||||
T operator*() const { return *reg; }
|
||||
|
||||
const T* operator->() const { return &*reg; }
|
||||
|
||||
~RAReg();
|
||||
|
||||
private:
|
||||
friend class RegAlloc;
|
||||
explicit RAReg(RegAlloc& reg_alloc, bool write, const IR::Value& value);
|
||||
|
||||
void Realize();
|
||||
|
||||
RegAlloc& reg_alloc;
|
||||
bool write;
|
||||
const IR::Value value;
|
||||
std::optional<T> reg;
|
||||
};
|
||||
|
||||
struct HostLocInfo final {
|
||||
std::vector<const IR::Inst*> values;
|
||||
size_t locked = 0;
|
||||
size_t uses_this_inst = 0;
|
||||
size_t accumulated_uses = 0;
|
||||
size_t expected_uses = 0;
|
||||
bool realized = false;
|
||||
size_t lru_counter = 0;
|
||||
|
||||
bool Contains(const IR::Inst*) const;
|
||||
void SetupScratchLocation();
|
||||
bool IsCompletelyEmpty() const;
|
||||
void UpdateUses();
|
||||
};
|
||||
|
||||
class RegAlloc {
|
||||
public:
|
||||
using ArgumentInfo = std::array<Argument, IR::max_arg_count>;
|
||||
|
||||
explicit RegAlloc(lagoon_assembler_t& as, std::vector<u32> gpr_order, std::vector<u32> fpr_order)
|
||||
: as{as}, gpr_order{std::move(gpr_order)}, fpr_order{std::move(fpr_order)} {}
|
||||
|
||||
ArgumentInfo GetArgumentInfo(IR::Inst* inst);
|
||||
bool IsValueLive(IR::Inst* inst) const;
|
||||
|
||||
auto ReadX(Argument& arg) { return RAReg<GPR>{*this, false, arg.value}; }
|
||||
auto ReadD(Argument& arg) { return RAReg<FPR>{*this, false, arg.value}; }
|
||||
auto ReadV(Argument& arg) { return RAReg<VPR>{*this, false, arg.value}; }
|
||||
|
||||
auto WriteX(IR::Inst* inst) { return RAReg<GPR>{*this, true, inst ? IR::Value{inst} : IR::Value{}}; }
|
||||
auto WriteD(IR::Inst* inst) { return RAReg<FPR>{*this, true, inst ? IR::Value{inst} : IR::Value{}}; }
|
||||
auto WriteV(IR::Inst* inst) { return RAReg<VPR>{*this, true, inst ? IR::Value{inst} : IR::Value{}}; }
|
||||
|
||||
auto ScratchGpr() { return RAReg<GPR>{*this, true, IR::Value{}}; }
|
||||
auto ScratchFpr() { return RAReg<FPR>{*this, true, IR::Value{}}; }
|
||||
auto ScratchVec() { return RAReg<VPR>{*this, true, IR::Value{}}; }
|
||||
|
||||
void DefineAsExisting(IR::Inst* inst, Argument& arg);
|
||||
|
||||
template<typename... Ts>
|
||||
static void Realize(Ts&... rs) {
|
||||
static_assert((mcl::is_instance_of_template<RAReg, Ts>() && ...));
|
||||
(rs.Realize(), ...);
|
||||
}
|
||||
|
||||
void UpdateAllUses();
|
||||
void AssertNoMoreUses() const;
|
||||
|
||||
private:
|
||||
template<typename>
|
||||
friend struct RAReg;
|
||||
|
||||
template<HostLoc::Kind kind>
|
||||
u32 GenerateImmediate(const IR::Value& value);
|
||||
template<HostLoc::Kind kind>
|
||||
u32 RealizeReadImpl(const IR::Value& value);
|
||||
u32 RealizeWriteImpl(const IR::Inst* value, HostLoc::Kind required_kind);
|
||||
|
||||
u32 AllocateRegister(const std::vector<u32>& order, size_t base_offset);
|
||||
void SpillGpr(u32 index);
|
||||
void SpillFpr(u32 index);
|
||||
u32 FindFreeSpill() const;
|
||||
|
||||
std::optional<HostLoc> ValueLocation(const IR::Inst* value) const;
|
||||
HostLocInfo& ValueInfo(HostLoc host_loc);
|
||||
HostLocInfo& ValueInfo(const IR::Inst* value);
|
||||
|
||||
lagoon_assembler_t& as;
|
||||
std::vector<u32> gpr_order;
|
||||
std::vector<u32> fpr_order;
|
||||
|
||||
static constexpr size_t GprCount = 32;
|
||||
static constexpr size_t FprCount = 32;
|
||||
static constexpr size_t GprOffset = 0;
|
||||
static constexpr size_t FprOffset = GprCount;
|
||||
static constexpr size_t SpillOffset = GprCount + FprCount;
|
||||
|
||||
std::array<HostLocInfo, GprCount + FprCount + SpillCount> hostloc_info;
|
||||
};
|
||||
|
||||
template<typename T>
|
||||
RAReg<T>::RAReg(RegAlloc& reg_alloc, bool write, const IR::Value& value)
|
||||
: reg_alloc{reg_alloc}, write{write}, value{value} {
|
||||
if (!write && !value.IsImmediate()) {
|
||||
reg_alloc.ValueInfo(value.GetInst()).locked++;
|
||||
}
|
||||
}
|
||||
|
||||
template<typename T>
|
||||
RAReg<T>::~RAReg() {
|
||||
if (value.IsEmpty()) {
|
||||
if (reg) {
|
||||
HostLocInfo& info = reg_alloc.ValueInfo(HostLoc{kind, reg->Index()});
|
||||
info.locked--;
|
||||
info.realized = false;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
if (value.IsImmediate()) {
|
||||
if (reg) {
|
||||
// Immediate was materialized into a scratch register
|
||||
HostLocInfo& info = reg_alloc.ValueInfo(HostLoc{kind, reg->Index()});
|
||||
info.locked--;
|
||||
info.realized = false;
|
||||
}
|
||||
} else if (!value.IsEmpty()) {
|
||||
HostLocInfo& info = reg_alloc.ValueInfo(value.GetInst());
|
||||
info.locked--;
|
||||
if (reg) {
|
||||
info.realized = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
template<typename T>
|
||||
void RAReg<T>::Realize() {
|
||||
if (write && value.IsEmpty()) {
|
||||
reg = T{reg_alloc.RealizeWriteImpl(nullptr, kind)};
|
||||
} else {
|
||||
reg = T{write ? reg_alloc.RealizeWriteImpl(value.GetInst(), kind) : reg_alloc.RealizeReadImpl<kind>(value)};
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace Dynarmic::Backend::LoongArch64
|
||||
28
src/dynarmic/src/dynarmic/backend/loongarch64/stack_layout.h
Normal file
28
src/dynarmic/src/dynarmic/backend/loongarch64/stack_layout.h
Normal file
@ -0,0 +1,28 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
|
||||
// SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <array>
|
||||
|
||||
#include "common/common_types.h"
|
||||
|
||||
namespace Dynarmic::Backend::LoongArch64 {
|
||||
|
||||
constexpr size_t SpillCount = 64;
|
||||
|
||||
struct alignas(16) StackLayout {
|
||||
s64 cycles_remaining;
|
||||
s64 cycles_to_run;
|
||||
|
||||
std::array<u64, SpillCount> spill;
|
||||
|
||||
u32 save_host_fpcr;
|
||||
u32 save_host_fpsr;
|
||||
|
||||
bool check_bit;
|
||||
};
|
||||
|
||||
static_assert(sizeof(StackLayout) % 16 == 0);
|
||||
|
||||
} // namespace Dynarmic::Backend::LoongArch64
|
||||
@ -36,6 +36,14 @@ inline void And(volatile u32* ptr, u32 value) {
|
||||
#endif
|
||||
}
|
||||
|
||||
inline u32 Exchange(volatile u32* ptr, u32 value) {
|
||||
#ifdef _MSC_VER
|
||||
return static_cast<u32>(_InterlockedExchange(reinterpret_cast<volatile long*>(ptr), value));
|
||||
#else
|
||||
return __atomic_exchange_n(ptr, value, __ATOMIC_SEQ_CST);
|
||||
#endif
|
||||
}
|
||||
|
||||
inline void Barrier() {
|
||||
#ifdef _MSC_VER
|
||||
_ReadWriteBarrier();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user